This invention relates to an operational amplifier of a type which comprises a differential cell transconductor input stage incorporating a current mirror provided with a pair of degenerative resistors and a gain stage directly driven by a transistor in said mirror.
The construction of amplifiers of the above type is usually completed by an output buffer connected after the gain stage and fed back to one of the signal inputs.
As is well known, in the specific field of application of this invention, there exists a demand for optimization of the amplifier input stage performance.
For that purpose, two so-called degenerative resistors are usually provided which are respectively associated with corresponding input and output legs of the current mirror incorporated to the input stage.
The current mirror is typically sized so that, in normal operation, the voltage across each of the resistors is approximately 200 mV. In this way, the collector/emitter voltage of the transistor which drives the gain stage can be held at a value of about 1.2 Volts, thereby preventing it from becoming saturated.
It may happen, however, that under some particular operating conditions, such as on the sudden occurrence of deep variations in the supply voltage, "breakdowns" appear in the npn or pnp junctions of the transistors incorporated to the input stage. This generates high breakdown currents which propagate to the current mirror and cause the transistor driving the gain stage to become saturated. The gain stage usually comprises a pair of transistors connected together into a Darlington configuration.
If this stage is driven into powerful conduction, it will in turn drive the output buffer to potentials close to the value of the negative supply voltage, e.g. the ground value.
If, as is often the case, the amplifier includes a feedback connection between its output and inverting input, then this input will also be driven to a potential close to the ground value, thereby holding the breakdown currents.
All this results in a "latch-up" state of the device, which is thereafter stuck for as long as power is present.
To avoid such a serious drawback, the prior art has proposed of connecting a diode in parallel with one of the degenerative resistors, namely that associated with the input leg of the current mirror.
In practice, this diode is formed by an npn transistor having its base shorted to the collector and connected between one end of said resistor and ground.
While being in several ways beneficial and substantially achieving its objective, this prior approach requires the provision of an additional element for which a suitable area must be reserved on the amplifier integrated circuit.
The underlying technical problem of this invention is to provide an improved amplifier which has such constructional and functional features as to overcome the limitations to prior art solutions, while minimizing the area to be occupied on the amplifier integrated circuit.
The solutive idea on which this invention stands is one of exploiting a parasitic diode associated with the degenerative resistors.
In the presently preferred embodiment, the technical problems are solved by an operational amplifier, of a type which comprises a differential cell transconductor input stage incorporating a current mirror provided with a pair of degenerative resistors and a gain stage, driven directly by a transistor of the mirror, has each degenerative resistor formed within an epitaxial well wherewith a parasitic diode is associated. Each diode is connected in parallel with its corresponding resistor to prevent the transistor which drives the gain stage from becoming saturated.
According to innovative teachings disclosed herein, there is provided: An integrated circuit, comprising: first and second matched branches, each the branch including respective first and second transistors, both the first transistors having respective control terminals which are connected in common, and at least one the second transistor being connected to receive an input signal; each the first transistor having a second terminal thereof connected through a respective degeneration resistor to a node which is common to the first and second branches; wherein the degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type; and wherein the well region overlies a buried layer of the second conductivity type which is more heavily doped than the well region; and wherein the well region and the buried layer overly a deeper region which is doped with the first conductivity type; and wherein the well region is laterally surrounded by a diffusion of the first conductivity type; and wherein no active devices are located in the well region with the resistors; and further comprising biasing circuitry connected to bias the first transistors at a level such that the junction between the first conductivity-type diffusion and the well region limits the voltage across the degeneration resistors and thereby prevents the transistors from going into saturation.
According to innovative teachings disclosed herein, there is provided: An integrated circuit, comprising: two matched bipolar transistors having respective bases thereof connected in common; each the transistor having an emitter thereof connected through a respective emitter degeneration resistor to a common node; wherein the degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type; and wherein the well region overlies a buried layer of the second conductivity type which is more heavily doped than the well region; and wherein the well region and the buried layer overly a deeper region which is doped with the first conductivity type; and wherein the well region is laterally surrounded by a diffusion of the first conductivity type; and wherein no active devices are located in the well region with the resistors; and further comprising biasing circuitry connected to bias the bipolar transistors at a level such that the junction between the first conductivity-type diffusion and the well region limits the voltage across the degeneration resistors and thereby prevents the transistors from going into saturation.
According to innovative teachings disclosed herein, there is provided: An integrated circuit, comprising: first and second matched branches, each the branch including respective first and second transistors, both the first transistors having respective control terminals which are connected in common, and at least one the second transistor being connected to receive an input signal; each the first transistor having a second terminal thereof connected through a respective degeneration resistor to a node which is common to the first and second branches; wherein the degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type; and wherein no active devices are located in the well region with the resistors; and further comprising biasing circuitry connected to bias the first transistors at a level such that the junction between the first conductivity-type diffusion and the well region limits the voltage across the degeneration resistors and thereby prevents the transistors from going into saturation.
According to innovative teachings disclosed herein, there is provided: An integrated circuit, comprising: two matched bipolar transistors having respective bases thereof connected in common; each the transistor having an emitter thereof connected through a respective emitter degeneration resistor to a common node; wherein the degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type; and wherein no active devices are located in the well region with the resistors; and further comprising biasing circuitry connected to bias the bipolar transistors at a level such that the junction between the first conductivity-type diffusion and the well region limits the voltage across the degeneration resistors and thereby prevents the transistors from going into saturation.
According to innovative teachings disclosed herein, there is provided: An operational amplifier of a type which comprises a differential cell transconductor input stage incorporating a current mirror provided with a pair of degenerative resistors, and a gain stage driven directly by a transistor in the mirror, wherein each degenerative resistor is implemented within an epitaxial well wherewith a parasitic diode is associated, and each the diode is connected in parallel with a corresponding one of the resistors.
The features and advantages of an amplifier according to this invention will be apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.